Publications

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A
Simão, J., and L. Veiga, "Adaptability Driven by Quality Of Execution in High Level Virtual Machines for Shared Environments", International Journal of Computer Systems Science and Engineering, vol. 28, no. 6: CRL, pp. 59-72, 2013. Abstract2013-csse-simao.pdf

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Simão, J., "An Adaptive Java Runtime Environment for Cloud Computing", Instituto Superior Técnico, 2014.
Sousa, D. G., J. M. Lourenço, E. Farchi, and I. Segall, "Aplicação do Fecho de Programas na Deteção de Anomalias de Concorrência", Proceedings of INForum Simpósio de Informática, Lisbon, Portugal, Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa, pp. 190–201, sep, 2012. Abstract2012-inforum-ds.pdf

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B
Silva, J. A., J. M. Lourenço, and H. Paulino, Boosting Locality in Multi-version Partial Data Replication, : Universidade Nova de Lisboa, 2014. 2014-silva.pdf
C
Simão, J., T. Garrochinho, and L. Veiga, "A checkpointing-enabled and resource-aware Java Virtual Machine for efficient and robust e-Science applications in grid environments", Concurrency and Computation: Practice and Experience, vol. 24, no. 13: John Wiley & Sons, Ltd, pp. 1421–1442, 2012. Abstract2012-ccpe-simao.pdfWebsite

Object-oriented programming languages presently are the dominant paradigm of application development (e.g., Java, .NET). Lately, increasingly more Java applications have long (or very long) execution times and manipulate large amounts of data/information, gaining relevance in fields related with e-Science (with Grid and Cloud computing). Significant examples include Chemistry, Computational Biology and Bio-informatics, with many available Java-based APIs (e.g., Neobio).Often, when the execution of such an application is terminated abruptly because of a failure (regardless of the cause being a hardware of software fault, lack of available resources, etc.), all of its work already performed is simply lost, and when the application is later re-initiated, it has to restart all its work from scratch, wasting resources and time, while also being prone to another failure and may delay its completion with no deadline guarantees.Our proposed solution to address these issues is through incorporating mechanisms for checkpointing and migration in a JVM. These make applications more robust and flexible by being able to move to other nodes, without any intervention from the programmer. This article provides a solution to Java applications with long execution times, by extending a JVM (Jikes research virtual machine) with such mechanisms. Copyright © 2011 John Wiley & Sons, Ltd.

Simão, J., and L. Veiga, "A Classification of Middleware to Support Virtual Machines Adaptability in IaaS", 11th International Workshop on Adaptive and Reflective Middleware (ARM 2012), In conjuntion with Middleware 2012: ACM, 2012. Abstract2012-arm-simao.pdf

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Simão, J., J. Singer, and L. Veiga, "A Comparative Look at Adaptive Memory Management in Virtual Machines", IEEE CloudCom 2013: IEEE, dec, 2013. Abstract2013-cloudcom-simao-c.pdf

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D
Vasques, J. L. V., and L. Veiga, "A Decentralized Utility-based Grid Scheduling Algorithm", 28th ACM Symposium On Applied Computing (SAC 2013): ACM, 2013. Abstract2013-sac-simao.pdf

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Lourenço, J. M., D. Sousa, B. C. Teixeira, and R. J. Dias, "Detecting concurrency anomalies in transactional memory programs", Comput. Sci. Inf. Syst., vol. 8, no. 2, pp. 533–548, 2011. Abstract2011-comsis.pdf

Software transactional memory is a promising programming model that adapts many concepts borrowed from the databases world to control concurrent accesses to main memory (RAM). This paper discusses how to support revertible operations, such as memory allocation and release, within software libraries that will be used in software memory transactional contexts. The proposal is based in the extension of the transaction life cycle state diagram with new states associated to the execution of user-defined handlers. The proposed approach is evaluated in terms of functionality and performance by way of a use case study and performance tests. Results demonstrate that the proposal and its current implementation are flexible, generic and efficient

Dias, R. J., J. C. Seco, and J. M. Lourenço, Detection of Snapshot Isolation Anomalies in Software Transactional Memory: A Static Analysis Approach, : Universidade Nova de Lisboa, UNL-DI-5-2011. 2011-dias.pdf
Martins, H., "Distributed replicated macro-components", Universidade Nova de Lisboa, 2013. 2013-helder_martins.pdf
Silva, J., Ditto – Deterministic Execution Replay for the Java Virtual Machine on Multi-processors, : Instituto Superior Técnico, 2012. Abstract2012-msc-ist-silva.pdf

In this work, we propose RATS, a middleware to enhance and extend the Terracotta framework for Java with the ability to transparently execute multi-threaded Java applications to provide a single-system image. It supports efficient scheduling of threads, according to available resources, across several nodes in a Terracotta cluster, taking advantage of the extra computational and memory resources available. It also supports profiling to gather application characteristics such as dispersion of thread workload, thread inter-arrival time and resource usage of the application. Profiling and clustering capabilities are inserted with the help of byte code instrumentations. We developed a range of alternative scheduling heuristics and classify them based on the application and cluster behavior. The middleware is tested with different applications with varying thread characteristics to assess and classify the scheduling heuristics with respect to application speed-ups. Results indicate that, for a CPU intensive application, it is possible to classify the scheduling heuristic based on application and cluster properties and also achieve linear speed ups. Furthermore, we show that a memory intensive application is able to scale its memory usage considerably when compared to running the application on a single JVM.

Silva, J. P. M., J. Simão, and L. Veiga, "Ditto – Deterministic Execution Replayability-as-a-Service for Java VM on Multiprocessors", ACM/IFIP/Usenix International Middleware Conference (Middleware 2013): Springer, dec, 2013. Abstract2013-middleware-silva.pdf

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E
Dias, R. J., J. M. Lourenço, and N. Preguiça, "Efficient and Correct Transactional Memory Programs Combining Snapshot Isolation and Static Analysis", Proceedings of the 3rd USENIX Conference on Hot Topics in Parallelism (HotPar'11), Berkeley, USA, Usenix Association, May, 2011. Abstract2011-hotpar.pdf

Concurrent programs may suffer from concurrency anomalies that may lead to erroneous and unpredictable program behaviors. To ensure program correctness, these anomalies must be diagnosed and corrected. This paper addresses the detection of both low- and high-level anomalies in the Transactional Memory setting. We propose a static analysis procedure and a framework to address Transactional Memory anomalies. We start by dealing with the classic case of low-level dataraces, identifying concurrent accesses to shared memory cells that are not protected within the scope of a memory transaction. Then, we address the case of high-level dataraces, bringing the programmer's attention to pairs of memory transactions that were misspecified and should have been combined into a single transaction. Our framework was applied to a set of programs, collected form different sources, containing well known low- and high-level anomalies. The framework demonstrated to be accurate, confirming the effectiveness of using static analysis techniques to precisely identify concurrency anomalies in Transactional Memory programs.

Dias, R. J., T. M. Vale, and J. M. Lourenço, "Efficient Support for In-Place Metadata in Java Software Transactional Memory", Concurrency and Computation: Practice & Experience, vol. 25, issue 17: Wiley, pp. 2394–2411, 2013. Abstract2013-ccpe.pdf

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Dias, R. J., T. M. Vale, and J. M. Lourenço, "Efficient Support for In-Place Metadata in Transactional Memory", Euro-Par 2012 Parallel Processing, vol. 7484, Rhodes, Greece, Springer Berlin Heidelberg, pp. 589–600, 2012. Abstract2012-europar.pdf

Implementations of Software Transactional Memory (STM) algorithms associate metadata with the memory locations accessed during a transaction’s lifetime. This metadata may be stored either in-place, by wrapping every memory cell in a container that includes the memory cell itself and the corresponding metadata; or out-place (also called external), by resorting to a mapping function that associates the memory cell address with an external table entry containing the corresponding metadata. The implementation techniques for these two approaches are very different and each STM framework is usually biased towards one of them, only allowing the efficient implementation of STM algorithms following that approach, hence inhibiting the fair comparison with STM algorithms falling into the other. In this paper we introduce a technique to implement in-place metadata that does not wrap memory cells, thus overcoming the bias by allowing STM algorithms to directly access the transactional metadata. The proposed technique is available as an extension to the DeuceSTM framework, and enables the efficient implementation of a wide range of STM algorithms and their fair (unbiased) comparison in a common STM infrastructure. We illustrate the benefits of our approach by analyzing its impact in two popular TM algorithms with two different transactional workloads, TL2 and multi-versioning, with bias to out-place and in-place respectively.

Rameshan, N., Efficient Thread Scheduling for Distributed Java VM, : Instituto Superior Técnico, 2012. Abstract2012-msc-ist-rameshan.pdf

In this work, we propose RATS, a middleware to enhance and extend the Terracotta framework for Java with the ability to transparently execute multi-threaded Java applications to provide a single-system image. It supports efficient scheduling of threads, according to available resources, across several nodes in a Terracotta cluster, taking advantage of the extra computational and memory resources available. It also supports profiling to gather application characteristics such as dispersion of thread workload, thread inter-arrival time and resource usage of the application. Profiling and clustering capabilities are inserted with the help of byte code instrumentations. We developed a range of alternative scheduling heuristics and classify them based on the application and cluster behavior. The middleware is tested with different applications with varying thread characteristics to assess and classify the scheduling heuristics with respect to application speed-ups. Results indicate that, for a CPU intensive application, it is possible to classify the scheduling heuristic based on application and cluster properties and also achieve linear speed ups. Furthermore, we show that a memory intensive application is able to scale its memory usage considerably when compared to running the application on a single JVM.

F
Simão, J., and L. Veiga, "Flexible SLAs in the Cloud with Partial Utility-driven Scheduling (Best-Paper Award Runner-up)", IEEE 5th International Conference on Cloud Computing Technology and Science (CloudCom 2013): IEEE, dec, 2013. Abstract2013-cloudcom-simao-a-best-paper-award-runner-up.pdf

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Dias, R. J., T. M. Vale, and J. M. Lourenço, "Framework Support for the Efficient Implementation of Multi-Version Algorithms", Transactional Memory: Foundations, Algorithms, Tools, and Applications: Springer, 2014. Abstractdias_vale_lourenco.pdf

Software Transactional Memory algorithms associate metadata with the memory locations accessed during a transaction’s lifetime. This metadata may be stored in an external table and accessed by way of a function that maps the address of each memory location with the table entry that keeps its metadata (this is the out-place or external scheme); or alternatively may be stored adjacent to the associated memory cell by wrapping them together (the in-place scheme). In transactional memory multi-version algorithms, several versions of the same memory location may exist. The efficient implementation of these algorithms requires a one-to-one correspondence between each memory location and its list of past versions, which is stored as metadata. In this chapter we address the matter of the efficient implementation of multi-version algorithms in Java by proposing and evaluating a novel in-place metadata scheme for the Deuce framework. This new scheme is based in Java Bytecode transformation techniques and its use requires no changes to the application code. Experimentation indicates that multi-versioning STM algorithms implemented using our new in-place scheme are in average 6× faster than when implemented with the out-place scheme.

I
Dias, R. J., T. M. Vale, and J. M. Lourenço, "In-Place Metainfo Support in DeuceSTM", Talk presented at the 2nd Euro-TM Workshop on Transactional Memory, Bern, Switzerland, 2012. Abstractwtm12-presentation.pptx_.pdf

Several Software Transactional Memory (STM) algorithms have been developed in the last few years. These algorithms differ in many different properties, such as progress and safety guarantees, contention management, etc. Some STM frameworks (DSTM2, DeuceSTM) were developed to allow the implementation and comparison of many different algorithms using the same transactional interface. The information required by an STM algorithm is either associated with the execution of a transaction (frequently referred as transaction descriptor), or associated with each memory location (or object reference) accessed within the transaction. The transaction descriptor is typically stored in a thread-local memory space and maintains the information necessary to validate and commit a memory transaction. The information associated with each memory location depends on the nature of the STM algorithm, which we will henceforth refer to as metadata, and may be composed by e.g. locks, timestamps or version lists. Since metadata is associated with each memory location, there are two main strategies regarding the location for storing such metadata: The metadata is stored either near each memory location (in-place strategy); or in a mapping table that associates the metadata with the corresponding memory location (out- place strategy). DeuceSTM is one of the most efficient STM frameworks available for the Java programming language and provides a well defined interface that allows to implement several STM algorithms using an out-place strategy. This work describes the adaptation and extension of DeuceSTM to support the in-place metadata strategy. Our approach complies to the following properties: Efficiency –- The STM implementation does not rely on an auxiliary mapping table, thus providing faster direct access to the transactional metadata; Non-transactional code is oblivious to the presence of metadata in objects, hence there is no performance overhead whatsoever for non-transactional code; Transactional code avoids the extra memory dereference imposed by the decorator pattern; Primitive types are fully supported, even in transactional code; And we provide a solution for fully supporting transactional N-dimensional arrays, which again impose no overhead on non-transactional code. Transparency –- The STM implementation automatically identifies, creates and initializes the necessary additional metadata fields in the objects; Non-transactional code is oblivious to the presence of metadata in objects, hence no code changes are required; The new transactional array types (supporting metadata for individual cells) are compatible with the standard arrays, hence not requiring any pre-/post- processing of the arrays when invoking standard or third-party non-transactional libraries. Performance benchmarking has confirmed that our approach for supporting in-place metadata in DeuceSTM, alongside with the existing out-place strategy, is a valid functional complement, widening the range of algorithms that can be efficiently implemented in DeuceSTM, enabling their fair comparison in a common infrastructure.

L
Martins, J., "Lightweight monitoring of transactional memory programs", Universidade Nova de Lisboa, 2013. 2013-joao_martins.pdf
M
Vale, T. M., A Modular Distributed Transactional Memory Framework, : Universidade Nova de Lisboa, 2012. Abstract2012-tiago_vale.pdf

The traditional lock-based concurrency control is complex and error-prone due to its low-level nature and composability challenges. Software transactional memory (STM), inherited from the database world, has risen as an exciting alternative, sparing the programmer from dealing explicitly with such low-level mechanisms. In real world scenarios, software is often faced with requirements such as high availability and scalability, and the solution usually consists on building a distributed system. Given the benefits of STM over traditional concurrency controls, Distributed Software Transactional Memory (DSTM) is now being investigated as an attractive alternative for distributed concurrency control. Our long-term objective is to transparently enable multithreaded applications to execute over a DSTM setting. In this work we intend to pave the way by defining a modular DSTM framework for the Java programming language. We extend an existing, efficient, STM framework with a new software layer to create a DSTM framework. This new layer interacts with the local STM using well-defined interfaces, and allows the implementation of different distributed memory models while providing a non-intrusive, familiar, programming model to applications, unlike any other DSTM framework. Using the proposed DSTM framework we have successfully, and easily, implemented a replicated STM which uses a Certification protocol to commit transactions. An evaluation using common STM benchmarks showcases the efficiency of the replicated STM, and its modularity enables us to provide insight on the relevance of different implementations of the Group Communication System required by the Certification scheme, with respect to performance under different workloads.

O
Vale, T. M., R. J. Dias, and J. M. Lourenço, "On the Relevance of Total-Order Broadcast Implementations in Replicated Software Transactional Memories", Multicore Software Engineering, Performance, and Tools, vol. 8063: Springer Berlin Heidelberg, pp. 49–60, 2013. Abstract2013-musepat.pdf

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